Quizzes

These should be submitted via ‘provide‘ from one of the Linux machines. Unless otherwise specified, they are due at 9:00am on the day of class. This is so I have time to review them and tailor our class to address questions and misunderstandings.

• Gates and logic functions (Quiz 1, due 1/22)

• Minimizing logic (Quiz 2, due 1/24)

• Multiplexers and FPGAs (Quiz 3, due 1/29)

• Combinationl circuit timing (Quiz 4, due 1/31)

• VHDL (Quiz 5, due 2/5)

• VHDL testbenches (Quiz 6, due 2/7 at class time)

• Latches and flip-flops (Quiz 7, due 2/12)

• Sequential logic with VHDL (Quiz 8, due 2/14)

• State machines (Quiz 9, due 2/19)

• There is no quiz 10

• Timing sequential logic (Quiz 11, due 2/28 at class time)

• Adders and other combinational circuits (Quiz 12, due 3/12 at class time)

• Memories (Quiz 13, due 3/14)

• No quiz 14

• More ARM assembly (Quiz 15, due 3/28 whenever)

• No quiz 16 (Caches)

• Virutal memory (Quiz 17, due 4/22)

• Modern processor smorgasboard (Quiz 18, due 4/24)