module reg4(wtdata,wtenable,wtaddr,reset,clk,rdaddr1,rdaddr2,rddata1,rddata2);

input [3:0] wtdata,wtaddr,rdaddr1,rdaddr2;
input       reset,clk,wtenable;
output [3:0] rddata1,rddata2;
reg   [3:0] rddata1,rddata2;
reg   [3:0] regfile [15:0];
integer i,j;

//reading process
always@(posedge clk)
begin
	rddata1 <= regfile[rdaddr1];
	rddata2 <= regfile[rdaddr2];
end

//writing process
always@(posedge clk)
begin
	if(reset)
		begin
			for(i = 0; i < 16; i = i + 1)
				regfile[i] <= 0;
		end
	else
		begin
			//for(j = 0; j < 16; j = j + 1)
				//if(j == wtaddr)
					//regfile[j] <= wtdata;
			if(wtenable)
				regfile[wtaddr] <= wtdata;
		end
end
endmodule