High-Speed Solid-State Imager Technology

Abstract

Electronically shuttered solid-state imagers are being developed for high-speed imaging applications. A 5 × 5 cm, 512 × 512 pixel, multiframe charge coupled device (CCD) imager has been fabricated that collects four sequential image frames at megahertz rates. To operate at fast frame rates with high sensitivity, the imager uses an electronic shutter technology designed for back-illuminated CCDs. The design concept and test results are described for the burst- frame-rate imager. CMOS-based solid-state imager technology has the promise for creating large-format X-ray detectors with short exposure times (100 ps to 1 ns). For example, CMOS transistors have switching speeds of tens of picoseconds needed for high-speed sampling circuits. A 64 × 64 pixel test circuit has been designed and fabricated in 0.18 μm CMOS technology to investigate high-speed imaging for large-format detectors. Several features have been integrated into the circuit architecture to achieve fast signal propagation with low skew and jitter for simultaneous pixel exposure times. These features include an H-tree clock distribution, single-edge trigger propagation with local and global repeaters, local exposure control, and current- switching sampling circuits. Also, a unique photodiode structure that has a fast response of less than 100 ps has been designed for bump-bond integration with the CMOS readout. The photodetector has features intended to maintain the fast performance up to peak X-ray fluences of 1017 photons/sec•cm2. The CMOS readout and photodiode design philosophy will be discussed.