To extract circuit models from your layout, we need to run Extraction. For this, click on Verify-> Extract in the layout editing window. Extractor window will show as shown in figure below.
After running extraction operation, if there are no errors, we will see the result as below.
And also a new file will be made in your cell directory. This is the extraction file of the inverter you draw as follows.
Open the extracted file. The file will be seen like this figure below. From this file, we are able to see all electrical connections and all parameters like capacitance and transistor sizes in the layout. Just try to click one node, then you will see all electrical connections of the node.
Now, you have electrically extracted data from your layout. What if you made any mistakes for connection, cadence will show you error messages.
Figure below is one of the examples.
To correct these errors, you can also use find option in the same manner as DRC.
If you cannot find them using find option, there is the other way we can use.
Open the extracted file in the library manager window. And then click on a suspicious node. Here, I click on í░ voutí▒ node as error messages said. The extracted view highlights all connections from vout node. Then we can see that vout is connected to gnd . To fix this, go to the layout editor, change the layout.
Layout Versus Schematic (LVS) Verification
We need to verify that it is really same as the circuit designed in schematic. For this, go to the Verify -> LVS. The Artist LVS window will pop-up.
Fill the Cell and View section as figure shown above. Please note that as the LVS is to compare schematic with extracted, the View name must be always schematic or extracted. To run the LVS, click on Run.
Cadence will show you new pop-up window as shown below.
Then, click on OK.
Please note, it means that cadence has finished LVS run, not pass LVS.
Once LVS job is successfully done, we need to check LVS output file whether the net lists from schematic and extracted view are matched each other or not. Click on output in the Artist LVS window. We will see the result file as figure below.
It must be no un-matched errors in the result.
Figure below is to explain how to fix LVS errors.
The output file shows that terminals are not matched even if it has same number of terminals.
To fix the error, click on Error display in the Artist LVS window as below.
Artist LVS Error Display window will pop-up.
Change Error Color to white one as show in figure.
And click on Display option, Here I choose First because the layout has only one error.
This is a result window.
The error is highlighted with white rectangle. The message says that í░Terminal out in the layout is not present in the schematicí▒. It means that in the layout, í░outí▒ is assigned as output name but in the schematic, the name is different with this. After checking the names, it turns out that the name in the schematic is vout, not out. Thus, to fix this, go back to the layout, change the name, run DRC, run extract, and do again LVS. If you pass LVS, you are done.