Professor and TA contact info and class meeting policy

• Instructor: Joel Grodstein, joel.grodstein@tufts.edu, https://www.eecs.tufts.edu/~joelg. Directions to my office are here.
• Instructor: Scott Taylor (Nvidia), staylo20@tufts.edu
• Class time/place: Tu/Th 3:00-4:15pm, Bromfield-Pearson 007
• TA: none
• For emergencies or private matters, please e-mail or see me directly.

Calendar and syllabus

• The class calendar is here.
• The syllabus is here.
• A flashy advertisement for the class is here.

Logistics for the labs

• The easiest way to do the labs is to use www.edaplayground.com. edaplayground.com allows you to upload your code and then run it on any several simulators. When your code has syntax errors, some simulators give more user-friendly error messages than others, and being able to easily switch simulators can be quite helpful. To use all of the simulators, you will have to validate your account by proving an e-mail address (either from Tufts or a company).
• Turn in your homework on the web with at this link. It will ask you for you Halligan username and password; these are just your usual Halligan ones that you use for the Windows PC lab (not your Tufts UTLN). Each team need only turn in one set of work for the entire team.

Course slides and video for main verification topics

• Course intro (lectures 1-2)
• Understanding a design (lectures 4-5)
• Overview of verification concepts (lectures 6-7)
• What goes into a testbench (lectures 10-11)
• Creating test stimulus (lectures 12-13)
• What is the right answer? (lectures 14-16)
• Test coverage (lectures 17-18)
• Creating a testplan (lectures 18-20)
• Post-silicon verification (lectures 21-23)

Course slides and video for SystemVerilog, the FIFO and the mesh

• SystemVerilog slides; (lecture 3) and 55 minutes total video: 1-5 (module), 6-12 (types), 13-17 (arrays), 18-22 (races), 23-30 (blocks), 31-end (static)
• FIFO slides; and 23 minutes total video for slides 1-6 (versions 1-3), 7-15 (v4), 16-end (empty/full)
• Mesh slides (lecture 8) and 36 minutes total video for slides 1-6 (intro), 6-15 (example), 16-22 (v2), 23-30 (2 packets), 30-36 (FIFOs) 37-end (mux selects)
• SystemVerilog classes and interfaces; slides

Labs

• FIFO lab #1 (ctl logic): assignment, fifo_1.sv and tb_fifo_1.sv
• FIFO lab #2 (ref model, scoreboard): assignment and solutions
• Mesh lab #1 (ctl logic): assignment, mesh_defs.sv, interface.sv, mesh_stop.sv, mesh_NxN.sv and tb_mesh_1.sv
• Mesh lab #2 (RCG): assignment and tb_mesh_2.sv
• Mesh lab #3 (tracker): assignment. Background slides and video: 1-8(the problem), 9-14(tracker v1), 14-17(tracker v2), 18-end(v3 and wrapup),
• Mesh lab #4 (coverage): assignment, tb_mesh_4.sv
• Final mesh lab: assignment, circuit picture, tb_mesh_challenge.sv, mesh_NxN_challenge.sv and mesh_stop_challenge.sv