CPU project resources

Simulating SystemVerilog on your computer

  • Download and install a recent release of the oss-cad-suite tools. This is a large package that includes everything you need to simulate designs and synthesize them for your FPGA.

  • If the install is correct, you should be able to run the following tools from a command line:

    • iverilog (Icarus Verilog, primary simulation tool)
    • verilator (Verilator simulator, gives better messages than Icarus)
    • gtkwave (GTKWave waveform viewer, for viewing simulation results)
    • yosys (Yosys synthesis)
    • make (GNU Make for automating builds)

Milestone 1: Getting started with the toolchain

Download the starter code here: Milestone 1

Milestone 2: ALU-only processor

Download the starter code here: Milestone 2

Complete the code for the following modules:

  • Program counter (pc.sv)
  • Program memory (progmem.sv)
  • Register file (regfile.sv)
  • Immediate extension (immextend.sv)
  • ALU (alu.sv) also available on VerilogWeb

Write testbenches to check your code! You should have at least one testbench for each module. An empty testbench file for the program counter is included in the starter code, along with a complete testbench for the processor.

Rather than assemble your complete processor all at once, it may help to build it up a little at a time:

  • Start with just the program counter and memory; make sure that the system steps through the instructions one at a time
  • Add the register file and immediate extension modules, check that the right values are coming out
  • Add the ALU and connect everything together

Milestone 3: Adding memory

Download the starter code here: Milestone 3

Directions are in the README.md file in the starter code.

Virtual machine image (3.5GB) for VirtualBox or VMWare Player

Milestone 4: Branches and jumps

Download the starter code here: Milestone 4

Directions are in the README.md file in the starter code.

Milestone 5: Running on the FPGA